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We have used laser thermal annealing (LTA) to activate shallow B and BF2 implants in p-type SOI wafers. Several characterization techniques have been employed in our investigations, such as SiPHER photoluminescence (PL) scans, Sheet resistance measurements (Rs), SIMS and AFM analyses. In sub-melt regime, there is no significant redistribution of implanted dopants; furthermore, BF2 implanted sample...
A newly developed surface analysis technique, which combines secondary ion mass spectrometry with angle-resolved X-ray photoelectron spectroscopy, was used to achieve more accurate results of the retained impurity doses and profiles for ultralow-energy implants, including conventional beamline implant and plasma immersion ion implantation (PIII). Using this method, it has been found that the B2H6...
49BF2+ implanted wafers were annealed in the temperature range of 900degC and 1100degC using a single wafer rapid thermal furnace for 30 sec to 1800 sec under N2 ambient at atmospheric pressure. Sheet resistance and its uniformity were measured. Boron and fluorine depth profiles at different annealing temperatures and times were analyzed using secondary ion mass spectroscopy (SIMS). The minimum...
We report on fabricated capacitors following B and BF/sub 2/ implantation with near-identical boron profiles as measured by SIMS. The C-V curves showed flatband shifts between the two implanted species which increase with the implant dose, up to 0.27 V for 1e14 cm/sup -2/. Modeling the processing with an interface trap model for boron in the case of BF/sub 2/ implant but not for B, gave good agreement...
In this paper is reported for the first time a rigorous physically based ion implantation damage model which successfully predicts both the as-implanted impurity profiles (SIMS) and the damage profiles (RBS) for a wide range of implant conditions for arsenic, boron and BF/sub 2/ implants. In addition, the amorphous layer thicknesses predicted by this new damage model for high dose implants are also...
The difficulties in device engineering increase rapidly as advanced circuits take up more portions in the design of low-power IC products. These new circuit designs enforce strict requirements on the deep-submicron FETs, particularly in the areas of: (1) properties of thin gate oxides, (2) control of short channel effects, (3) doping profiles to reduce subthreshold slope and back-gate bias coefficient,...
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