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Amorphous, substoichiometric silica nanowires (NWs) can be grown on gold-coated silicon wafers by high-temperature annealing in an inert ambient with a low residual partial pressure, consistent with conditions required for the active oxidation of the underlying Si substrate. The vapor precursor required for NW growth is volatile SiO obtained directly from the reaction between the substrate...
In recent years, Si and Si1-xGex nanowires have received tremendous attention especially for their potential in optical and electronics devices. With the thermal oxidation technique, they are well compatible with current CMOS-based electronic devices and thus can be building blocks for nanoscale device applications ranging from biological sensors to nanoelectronics to catalyst-assisted growing techniques...
We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET IDSAT = 825/950 μA/μm (circumference-normalized) or 2592/2985 μA/μm (diameter-normalized) at supply voltage VDD = 1 V and off-current IOFF = 15 nA/μm. Superior NW uniformity is obtained...
We propose a novel technique for top-down fabrication of Si nanowire (SiNW) field effect transistors (FETs) using active oxidation of the Si channel. The width and line edge roughness of the SiNW channel were simultaneously reduced by active oxidation to 2.8 nm and 1.97 nm (3-σ), respectively. Device performance of ultra-thin SiNW FETs with atomically controlled nanowire-size and nanowire-shape is...
The growth of porous ZnO nanowires (NWs) by thermal oxidation of ZnS NWs in air was studied. The ZnS NWs were first synthesized by thermal evaporation of ZnS powder at 1100??C in Ar. On subsequent annealing in air, the ZnS NWs transformed to porous ZnS-ZnO core-shell NWs and porous ZnO NWs at 600-700??C and 700-750??C, respectively. Higher annealing temperature suppressed the formation of porous structure...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
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