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This paper describes a System-on-Chip platform architecture for low power high performance Digital Signal Processing intensive applications. The platform is based on the AMBA SoC bus protocol and incorporates a novel interfacing scheme which utilizes the bus hierarchy within AMBA in order to allow single and multiple high performance DSP Intellectual Property cores to be integrated to the SoC platform...
Summary form only given. Deep submicron technologies have allowed modern SOC's to be composed 100s of distinct IP blocks ranging from IO interfaces, to network-on-chip, to processing elements. These SOCs often take years from concept to production. Despite this huge silicon design cost, actual system design costs are dominated by software development often happing at multiple customers for each SOC...
A key challenge in the design of low power digital systems is the fast and accurate estimation of power dissipation. In this paper, we present a look-up-table (LUT) based power macromodeling technique for digital signal processing (DSP) architecture in terms of the statistical knowledge of their primary inputs/ouputs. During the power estimation procedure, the sequence of an input stream is generated...
A key challenge in the design of low power digital systems is the fast and accurate estimation of power dissipation. In this paper, we present a look-up-table (LUT) based power macromodeling technique for digital signal processing (DSP) architecture in terms of the statistical knowledge of their primary inputs/ouputs. During the power estimation procedure, the sequence of an input stream is generated...
This paper presents an intellectual property (IP)-based system-on-chip (SoC) synthesis framework focusing on how to select IPs from different sources and how to integrate the selected IPs using on-chip buses. In order to synthesize an on-chip bus-based SoC architecture using IPs with imprecise design costs, we propose a possibilistic mixed integer linear programming (PMILP) model, which is converted...
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