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The general objective of our work is to investigate the area and power-delay performances of low-voltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits. A new hybrid style full adder circuit is also presented. The sum and carry generation circuits of the proposed full adder are designed with hybrid logic styles. To operate at ultra-low supply...
There is a tremendous need for miniaturization as well as low power consumption in many processor architectures, especially when they are used in portable equipment. In this context, the design of low-power DSPs (digital signal processors) is of utmost importance. A clever means of achieving this is by the use of pass logic circuits in these designs, but switching activity is found to be a major contributor...
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