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The Envelope Elimination and Restoration (EER) technique has attracted significant attention recently because of its high efficiency under back-off operation. Memoryless Digital Predistortor (DPD) is indispensable for an EER power amplifier (PA) because of the EER PA's strong nonlinearity due to the dynamic power supply voltage. However, performance of the memoryless DPD is significantly degraded...
In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit 1GSPS at 1.8 V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further,...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
A novel configuration for a Brillouin distributed fiber sensor based on Brillouin optical time-domain analysis is proposed. This configuration eliminates many intensity noise issues found in previous schemes. Resolution of 7 m all over a 47 km single-mode fiber was achieved and resolution down to 30 cm in a few kilometer fiber. Noise reduction makes possible measurements with a 16 times averaging.
Optical communication systems based on dense wavelength division multiplexing (DWDM) would benefit from the ability to adjust the operating wavelength of a laser transmitter. Previous attempts, including thermal adjustment, etalon based wavelength locking, and various types of optical frequency and phase locked loops such as the Pound-Drever-Hall technique suffer from weaknesses including sensitivity...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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