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Flash converters have high speed conversion rate compared to other types of Analog to digital converter (ADC). As precision increases, Flash ADC requires large number of comparators compared to other ADCs. Hence, the increase in chip area, power consumption and cost of Flash converters makes trade off for many applications. So, the low power Flash ADC is aimed to be designed with less number of low...
In this paper, a novel readout scheme for the one-transistor one capacitor (1T-1C) DRAM will be introduced. The scheme depends on charging the bitline as well as the cell-storage capacitance to a certain level and comparing the charging current with a reference current to disclose the stored data. The factors affecting the sense margin will be discussed. The proposed readout scheme will be verified...
The Adder is the important part in any processor/controller design. Till date there are a plenty of 1-bit full-adder circuits which have been proposed and designed. In this paper we have a analytic and comparative description of various full adder circuits, considering various constraints like power consumption, speed of operation and area. The circuits are designed in the virtuoso platform, using...
As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the...
Domino logic circuits are most often used in high performance designs such as microprocessors because of high speed and less area over the static logic. But these domino logics suffer from high power dissipation and low noise tolerance. In this paper the earlier proposed techniques to reduce power consumption of Domino logic such as Dual Threshold Voltage (DTV), Dual Threshold Voltage-Voltage Scaling...
Leakage currents are one of the major design concerns in Deep sub-micron (DSM) technology due to rapid integration of semiconductor industries by reducing the transistor size. Many parameter has been reduces with technology scaling such as Threshold voltage, oxide thickness, channel length and supply voltage (Vdd) has been reduced to keep power consumption under control. As a consequence, the transistor...
Dynamic domino logic circuits are used for high system performance. The dynamic circuits offer superior speed and power dissipation over static CMOS circuits. But these circuits suffer from limitations such as charge leakage, noise and charge sharing. This article provides analysis of the different keeper topologies on pseudo domino logic circuits with reference to power dissipation. The circuit simulations...
Dynamic logic style is mainly used for high fan in and high performance circuits because of its smaller area and fast superior speed. This style comes with a problem of low noise margin which makes it more susceptible to noise than static CMOS circuits. It also faces some charge sharing and leakage problems. A small amount of noise at the input can cause an undesirable change at the output. Domino...
CMOS logic is extensively used in VLSI circuits but due to scaling of technology, the threshold voltage of the transistors used in CMOS circuits decrease which cause an increase in leakage power. Dynamic power consumption, which is proportional to square of supply voltage VDD further adds to the overall power dissipation. This results in low battery life of mobile devices. In this brief, a novel method...
This paper presents some proposed and new techniques in comparison to a traditional one for register-transfer level (RTL) circuits. The traditional technique focuses on killing glitches in both the control and data path parts of the circuit to reduce power consumption. By analyzing and simulating the generation and propagation of glitches in some benchmark circuits, we found out some issues when killing...
This paper presents results of analyses of full adders structures to build of low-power adders for specific data. At first four 1-bit full adder cells were selected from literature, designed in UMC 180nm technology and simulated for assessment of theirs energetic and time parameters. Extended power consumption model, taking into consideration input vector changes, was used, giving more accurate values...
Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS...
Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS...
Thermal issues is an important challenge in NanoCMOS chips. High temperatures can reduce the reliability, so it is important to reduce power consumption to improve reliability. It is necessary a change in physical design paradigms to reduce the needed amount of transistors to perform one task. This work shows a new approach to reduce the amount of transistors by using complex gates and a new set of...
Self-boost-programming for ferroelectric-NAND (Fe-NAND) flash memory was investigated by using a miniature memory cell array, which could reduce bit-line voltages for programming. As the best performance, 0.5V bit-line-voltage programming with 10μs-pulse width was successfully demonstrated. This study indicated that the Fe-NAND flash memory can be operated by much lower power consumption than that...
An energy efficient logic which is resistant to differential power analysis attacks is proposed in this paper. It is used to provide security to several encrypting devices like smart cards. The combination of dual-rail logic for security and adiabatic approach for low power, leads to the proposed energy efficient secure logic style. The advantage of the proposed logic over the existing secure logic...
This paper presents a 0.5 V pseudo fully differential CMOS op-amp with rail-to-rail input/output swing. The circuit is designed based on class AB input and output stages. In the design, quasi FGMOS transistors are employed. The proposed amplifier is designed using 0.18 μm CMOS technology, and the simulation results show rail-to-rail input and output swings. The open-loop gain and gain-bandwidth product...
A 1.2V 10bit 83MS/s pipeline ADC implemented in 130nm CMOS Technology is described with practical design techniques and considerations. Emphasis was placed on noise analysis and capacitance optimization, which helps to reduce both die area and power consumption. Design experiences of operational amplifier, comparator and switches were also shared. This design achieves INL and DNL of +0.65/-0.53LSB...
A novel low-power successive approximation register is proposed. The new register is based on gating the clock when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 14 bits has been designed up to the layout level with 1V power supply in 90nm CMOS technology and...
Sub-threshold operation has been proved to be successful to achieve minimum energy consumption. It is well known that the sub-threshold device sizing is different from super-threshold due to different current behavior. The previously reported sub-threshold sizing methods assume that the current is proportional to the transistor width. However, we have found that the inverse narrow width effect has...
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