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In this paper, the modeling and analysis of power supply noise effects on analog-to-digital converter (ADC) with chip-Package-PCB hierarchical power distribution network (PDN) is proposed. Especially, this research is focused on the PDN structure, which includes power/ground Through-Silicon-Via (TSV) for the case study of various PDN structures. The analysis was progressed with a frequency range from...
In this paper, the effect of power supply noise imbalance on 900 MHz differential low noise amplifier (LNA) output is investigated. Chip and package (PKG) power distribution network (PDN) are modeled with lumped components to estimate the power supply noise imbalance. Also an equivalent circuit of differential LNA is modeled to estimate the noise voltage at differential LNA output and verified through...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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