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The S/D-to-silicide contact resistivity is accurately extracted from state-of-the-art CMOS devices based on a new extraction methodology featuring parasitic and geometric corrections. With this sensitive extraction methodology and advanced S/D formation processes, low 10-8 Omega-cm2 CMOS contact resistivity meeting 2007 ITRS projection for sub-20 nm technologies is demonstrated. In the quest for less...
Complete modelling of electrically controlled nanoscale gas sensors with Poisson, Wolkenstein, Fokker-Planck and continuity is presented. Based on a plausible Drift explanation we developed suitable models for sensitivity control and operational modes. An onset for CMOS-complying annealing procedures is given.
While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and SRAM cells. FinFET SRAMs are shown to have excellent VDD scalability (SNM=185 mV at 0.6 V), enabling sub-32 nm low-voltage design.
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Graphene is a possible candidate for advanced channel materials in future field effect transistors. This presentation gives a brief overview about recent experimental results in the field of graphene transistors for future electronic applications.
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