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In this paper the Parameters of a Double Layer Super Capacitor (DLC) Bank are experimentally identified online using Recursive Least Squares (RLS). In order to extract the signals suitable for the RLS a proper signal processing system has been implemented. Results have been verified with those obtained with an off-line common technique applied to the 2-branch model of the DLC.
This paper presents a dynamic model for on-chip inverting capacitive charge pumps driven by two non-overlapping clock signals. The model implements the charge reusing technique to mitigate the efficiency loss due to the charge and discharge process of the parasitic capacitances. Validation with both circuit-level simulations and experimental results is shown, demonstrating high accuracy. An application...
In this paper, we present an improved plane-pair model for power distribution system modeling using the partial element equivalent circuit approach. The modified nodal analysis with a sub-meshing strategy leads to an efficient and accurate circuit solution in both the frequency domain and time domain.
Finding a suitable topology and Noise-transfer-function for higher order Incremental Delta-Sigma ADCs is a complex task. Estimating the performance of the ADC taking the circuit nonidealities into account by simulation requires sophisticated modeling and significant computing resources. Even with complex models, taking into account all nonidealities is not possible. This work proposes a completely...
A mathematical model of short-term arterial pressure regulation by the carotid baroreflex was integrated with a simple cardiovascular model to study the interactions between the baroreguation and the pusating heart. The cardiovascular system was modeled as an electric circuit, consisting of the left ventricle as a time-varying capacitance, the systemic circulation as a four-element RLC circuit, the...
The speeds of computers need to increase. A limitation to increasing this speed is the layout design of printed circuit boards (PCB's). One of the critical limiting factors of the PCB is the orientation of differential capacitors with respect to one another. This paper determines the optimal orientation of these capacitors in order to reduce the return loss (DS11) from crosstalk as the speeds of computers...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
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