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This paper presents a design methodology for the tuning of a class-D half-wave resonant rectifier with a parallel LC resonant tank input network. Class-D resonant rectifiers offer numerous advantages at high operating frequencies that are leveraged here in the design of a high-voltage rectifier. The absence of a systematic design process, however, has been a limiting factor. Designers have been relying...
Multistring arrays of LED are increasingly used for high-luminance lighting applications. The parallel connection of multiple LED strings, however, gives rise to the issue of current balancing between the strings, as a common voltage applied to them does not guarantee an equal current sharing due to the manufacturing spread in electrical properties. In relation to the need of current balancing, the...
In this paper we discuss some aspects of antennas in real designs in SOI technology, and show how the concepts manifest themselves in actual chips, where second-order effects such as resistance and the details of the processing sequence can play an important role. We also discuss the ramifications of a more recent technique which inserts bulk contacts into the SOI design, thereby imposing a bulk-like...
CMOS latch-up has historically been a problem in bulk CMOS processes through a parasitic pnpn structure formed by parasitic pnp and npn bipolar transistors. In application systems, latch-up is a dominant failure mode that causes either soft failure due to a loss of data logic states or destructive failure of the system. In this paper, the authors focused on cases of I/O VDD to core VDD latch-up and...
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