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The features and limitations of both SRAM and NVM (non-volatile memory) technologies have led the researchers to study SRAM-NVM way-based hybrid last level caches (LLCs). Since large leakage power consumption of SRAM allows including only few SRAM ways, the small write-endurance of NVM may still lead to small lifetime of these hybrid caches. We propose AYUSH, a technique for improving lifetime of...
Phase change memory (PCM) is non-volatile memory that is byte-addressable. It is two to four times denser than DRAM, orders of magnitude better than NAND Flash memory in read latency, and 10 times better than NAND Flash memory in write endurance. However, it still limits the number of write operations to at most $10^6$<alternatives><inline-graphic xlink:type="simple" xlink:href="on-ieq1-2419660.gif"/> </alternatives>...
Due to scalability and energy consumption, the use of DRAM as the only main memory technology in modern computers is becoming increasingly less appealing. Researchers have proposed combining DRAM and non-volatile memory (NVM) in main memory to increase capacity and reduce energy consumption. Due to its architectural simplicity, software-managed hybrid memory is a promising way to incorporate NVM....
Non-volatile memory (NVM), such as PCM, STT-MRAM, and ReRAM, makes it possible to integrate secondary storage into main memory. This integration reduces I/O access times to typically slow block devices; however, it is unrealistic to construct a large capacity main memory with a single NVM at this time, because NVM have disadvantages regarding write access. Combining NVM and other memory devices is...
This paper presents a novel concept called write intensity prediction for energy-efficient non-volatile caches as well as the architecture that implements the concept. The key idea is to correlate write intensity of cache blocks with addresses of memory access instructions that incur cache misses of those blocks. The predictor keeps track of instructions that tend to load write-intensive blocks and...
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