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This paper presents a 10-bit 50MS/s successive approximation register (SAR) ADC with low input capacitance that uses an on-chip resistive ladder to arrange a new switching scheme. The proposed arrangement not only reduces the total input capacitance, but also performs the predictive capacitor switching sequence to further reduce the power consumption. Therefore, the proposed SAR ADC has the features...
In this paper, an area-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with a dithering Vref is proposed. It reuses the capacitive array with the reconfiguration of Vref to Vref ± ΔV for reducing dramatically the ADC's area. The 2n resolution is achieved by the n bit SAR-ADC. To verify the proposed scheme, the proposed SAR ADC is implemented in a TSMC 0.18 μm 1P6M...
In this paper, a 7 stage switched capacitor pipelined ADC is described. This ADC is designed to achieve 12-bit resolution at the speed up to 125MSPS, which uses a fully differential switched capacitor pipelined architecture. This ADC includes an input broadband buffer, a high performance sample-and-hold amplifier (SHA) front end, and 7 pipelined sub-ADC stages. A double poly triple metal 0.35 μm BiCMOS...
This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually...
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