The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
An SoC with ARM® Cortex™-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted Channel™ (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MHz speed via VDD scaling and body biasing. Alternatively DDC technology demonstrates 35% speed increase at matched power. The results hold across process corners...
This paper describes ARM3, a second generation RISC microprocessor. The device is a 32-bit CPU, with a 4KByte on-chip cache and a co-processor interface. Two asynchronous clocks are used to ensure that the speed of internal cache cycles is not compromised by the speed of the external memory system, thus permitting the device to be used with low-cost DRAMs. The chip has been fabricated on a 1.5??m...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.