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Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained from Application-Specific Integrated Circuits (ASICs), while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers and to master hardware...
High-level data link control (HDLC) procedure is one of the most important protocols in digital communications. This paper analyzes the methods of HDLC procedure implementation commonly used nowadays, and points out their defects. We propose a new hardware implementation of HDLC procedure based on Field Programmable Gates Array (FPGA), and especially illustrate how to generate frame check sequence...
A system module of reactive power measurement is proposed on the basis of analyzing the mathematic model in this paper. A FFT intelligence property (IP) core is designed to estimate the amplitude and phase of harmonic. Two multipliers and a subtraction also are designed to calculate reactive power. Transposing circuit is applied to fix the data in order to reduce error of the system. An adder module...
The principles of orthogonal frequency division multiplexing (OFDM) modulation have been around since 1960s. However, recently, the attention toward OFDM has grown dramatically in the field of wireless and wired communication systems. This is reflected by the adoption of this technique in applications such as digital audio/video broadcast (DAB/DVB), wireless LAN (802.11a and HiperLAN2), broadband...
In wireless sensor networks, the data transmitted from the sensor nodes are vulnerable to corruption by errors induced by noisy channels and other factors. Hence it is necessary to provide a proper error control scheme to reduce the bit error rate (BER). Due to the stringent energy constraint in sensor networks, it is vital to use energy efficient error control scheme. In this paper, we focus our...
Lossless data compression algorithms are widely used by data communication systems and data storage systems to reduce the amount of data transferred and stored. GZIP is a popular, patent-free compression program that delivers good compression ratios. This paper presents hardware implementations for the LZ77 encoders and Huffman encoders that form the basis for a full hardware implementation of a GZIP...
This paper describes the implementation for a basic fuzzy logic controller in Very High speed integrated-circuit Hardware-Description Language (VHDL). It is not intended as an introduction to fuzzy logic control methodology; instead, we try to demonstrate the implementation of a fuzzy logic controller through the use of the VHDL code. Use of the hardware description language (HDL) in the application...
HDL2GDS is a fully automated ASIC digital design flow capable of transforming VHDL or Verilog integrated circuit specifications into a corresponding GDSII mask layout file. With one command the RTL or behavioral-level HDL specification is synthesized, a simple floorplan is generated, blocks and macros are placed, power is routed, standard cells are placed, a clock-tree is generated, hold-time violations...
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is dedicated to generate two context-symbol pairs per clock cycle. A novel method called dynamic significance state restoring (DSSR) allows reduction of on-chip memories. The overall design is described in VHDL and synthesized...
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