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Square root is one of the fundamental arithmetic operations in signal and image processing algorithms. This article presents a novel pipelined architecture to implement N-bits fixed point square root in FPGA using non-restoring algorithm. Pipelining hazards were avoided by modifying the non-restoring algorithm resulting in a 30% improved latency time. Furthermore, the proposed architecture is flexible...
Security devices are vulnerable to differential power analysis (DPA) that reveals the key by monitoring the power consumption of the circuits. In this paper, we present the first DPA attack against an FPGA implementation of the camellia encryption algorithm with all key sizes and evaluate the DPA resistance of the algorithm. The Camellia cryptographic algorithm involves several different key-dependent...
To secure cryptography hardware implementation many works are focusing on side-channels attacks. For such attacks, several different countermeasures can be done at different levels abstraction. But all published countermeasures lead to a significant area and power consumption overhead. In this paper, we present a new countermeasure against DPA attack which also leads to very small implementation compared...
This paper proposes an FPGA based methodology to assess the energy efficiency of application specific processors (ASIPs). This methodology is applied to a video processing algorithm, the motion compensated frame rate conversion (MC-FRC). Previous work has shown that designing a specific instruction set can enhance the performance with a speed-up of more than 80 fold. The purpose of this work is to...
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