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Because of their excellent error correction performance, Low-Density Parity Check Codes (LDPC) have become the most widely used technique for forward error correction in almost all modern communications applications. This paper introduces an FPGA implementation of a partial parallel, flexible LDPC decoder based on the Min-Sum decoding algorithm. The suggested architecture uses a combination of unicast...
Powerful forward error correction codes such as quasi-cyclic low density parity check (QC-LDPC) are required in next-generation coherent optical communication systems [1]. This work describes the design and experimental verification of a high net coding gain (NCG), low complexity QC-LDPC code. Towards this end, we develop a field programmable gate array (FPGA) based platform specially designed for...
Fixed-complexity Sphere Decoder (FSD) is a recently proposed technique for Multiple-Input Multiple-Output (MIMO) detection. It has several outstanding features such as constant throughput and large potential parallelism, which makes it suitable for efficient VLSI implementation. However, to our best knowledge, no VLSI implementation of FSD has been reported in the literature, although some FPGA prototypes...
In this paper, a reduced complexity Low-Density Parity-Check (LDPC) decoder is designed and implemented on FPGA using a modified 2-bit Min-Sum algorithm. Simulation results reveal that the proposed decoder has improvement of 1.5 dB Eb/No at 10-5 bit error rate (BER) and requires fewer decoding iterations compared to original 2-bit Min-Sum algorithm. With a comparable BER performance to that of 3bit...
With increasing demand for different data rates and services for communication systems, reconfigurability is of utmost importance. Field Programmable Gate Arrays (FPGAs) provide the flexibility in operation and function by a simple change in the configuration bit stream. Low complexity turbo-like codes based on simple two-state trellis or simple graph structure results in decoder with low complexity...
A modified algorithm for two-dimensional TPC decoding is proposed to reduce the wrong frame rate in the (16,11,4)2 Turbo Product Code (TPC) decoding in this paper. It is based on the hard decision decoding, including a chooser and a parallel decoding architecture that one is column-row and the other is row-column. The Monte-Carlo simulation shows that 30% wrong frame is eliminated and the implementation...
Turbo code is a class of convolutional codes which have great deal of interest as they attain the ultimate limits of the capacity of communication channel. They are known as ??The ultimate Error Control Codes?? which made them move rapidly from research laboratories to practical applications throughout the world. The use of these codes has been proposed for several applications where highly reliable...
Structured LDPC codes enable low-complexity decoding as well as efficient implementation of encoder reducing the complexity down to the order of the number of parity-check bits. Construction of structured LDPC codes is based on combinatorial approaches such as balanced-incomplete block-design (BIBD) and finite fields to design quasi-cyclic LDPC (QC-LDPC) codes. Well designed QC-LDPC codes can perform...
We implemented a soft-decision decoder of (204,188)-Reed-Solomon code, which is used widely in standards for satellite, terrestrial, and other broadcasting systems. The decoder employs a list decoding technique using iterative adaptive belief propagation and bounded distance decoding. One decoded word is chosen from the list by MAP decoding, and some ideas are applied to reduce its complexity. When...
In this paper, the use of single-error-correcting Reed-Solomon (RS) product codes are investigated in an ultra high-speed context. A full-parallel architecture dedicated to the turbo decoding process of RS product codes is described. An experimental setup composed of a Dinigroup board that includes six Xilinx Virtex-5 LX330 FPGAs is employed. Thus, a full-parallel turbo decoding architecture dedicated...
This paper presents the FPGA implementation of a number of popular decoding algorithms for a regular rate-1/2 low density parity check code with block length 504 bits. The so-called min-sum (MS) algorithm and two of its variants, known as MS with successive relaxation (SR-MS) and MS with unconditional correction (MS-UC), are implemented. We implement the algorithms on a Xilinx XC2VP100 FPGA device...
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