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Architecture of fast data recovery was introduced into the design of the digital receiver in UHF RFID Reader. The data should be recovered in a short time for the next step of decoding. Rich synchronizing information in Miller coding was used to improve the quality of decoding in a poor situation. The architecture of fast data recovery consisted of edge detector, period measure, cnt_syn and data recovery...
In the paper the implementation on reconfigurable hardware of a Sugeno type neuro adaptive fuzzy inference system is proposed to be presented. The pipeline and parallel pipeline architecture play an important role in modelling the algorithm for the FPGA based implementation. In order to design the pipeline-parallel model of the controller two different methods were used: high level synthesis tool...
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