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An original and modern integrated current sensor is designed and presented in this paper. It can provide a sense current proportional to an output current available to the microcontroller via an external resistor. The ratio between output and sense current is modeled and simulated. The errors between the two currents increase in low currents domain. A solution consisting in a gate back regulation...
A low drop-out (LDO) voltage regulator with high power supply rejection ratio (PSRR) and enhanced transient response is presented in this study. The proposed idea is to apply a replica circuit that injects current into the second stage of the error amplifier. The LDO is being fabricated in Magna Chips CMOS Technology. The regulated output voltage of the LDO is 1V with the power supply voltage of 1...
This paper presents a technique to control the output voltage of series-parallel (SP) topology inductive power transfer (IPT) system by using only a primary side controller which reduces cost, size, complexity and loss compared to the conventional IPT dual-side controller. The duty cycle of the inverter output voltage is controlled by a controller located in the primary side which keeps the DC output...
Along with the development of Long term evolution (LTE) communication system, higher linearity and efficiency of base station power amplifier required. Although, Conventional Doherty amplifier base station can't meet this requirement. For the first time, This is the first use of Envelope tracking (ET) technology is used to dynamically control the gate voltage of Doherty power amplifier peak amplifier:...
Along with the development of Long term evolution (LTE) communication system, higher linearity and efficiency of base station power amplifier required. Although, Conventional Doherty amplifier base station can't meet this requirement. For the first time, This is the first use of Envelope tracking (ET) technology is used to dynamically control the gate voltage of Doherty power amplifier peak amplifier:...
A low dropout (LDO) regulator is designed in this paper. By adopting a slew rate enhancement circuit, the slew rate of the LDO output is obviously improved when the load current is suddenly switched from low to high. Moreover, employing a simple bias circuit, the architecture of the LDO regulator is simple, and can be fabricated by conventional CMOS technology. The LDO regulator is designed and simulated...
This paper presents a dual-buck full-bridge inverter (DBFBI) with the sinusoidal pulse width modulation (SPWM) and single current sensor. Shoot-through problem does not exist. All the power devices and filter inductors operate at each half line cycle, thus the efficiency can be increased. Only one switch works at high frequency when the reference current and the output voltage have the same polarity,...
High power IGBTs are widely used in wind power generation systems. An advanced IGBT gate driver with Dynamic Voltage Rise Control (DVRC) is used to suppress the turn-off over-voltage of the IGBT. Mass simulations are done to evaluate the performance, showing influence of the DVRC parameters, in order to select the right parameters for applications.
Power consumption has become one of the most important differentiating factors for semiconductor products. Voltage is the strongest handle for managing chip power consumption. We look in detail at some of key power management techniques such as power gating, adaptive voltage scaling and active body-bias that leverage voltage as a handle. We discuss the implications of power management architecture...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
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