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This paper presents a 13-bit fully-differential successive approximation register analog-to-digital converter with a hybrid DAC that is suitable for sensor applications. An innovative dithering plus averaging technique is developed around this originally-designed 10-bit ADC to make it possible to attain an effective resolution of 13 bits in a configurable fashion without calibration. The ADC has a...
This paper describes a low-power 25-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. The ADC employs a novel low-energy and area-efficient tri-level switching scheme in the DAC. Compared to the conventional SAR ADC, the average switching energy and total capacitance are reduced by 97% and 75%, respectively. Asynchronous design is implemented...
A 6 bit and a 7 bit successive approximation register (SAR) analog-to-digital converter (ADC) with conversion rates of up to 80 MS/s are presented in this paper. They will be used in an impulse-radio ultra-wideband (IR-UWB) receiver. The architecture with a switched-capacitor (SC) digital-to-analog converter (DAC) is applied due to its low power consumption. The 6 bit analog-to-digital converter applies...
New architectures are proposed for the realization of micro-power analog-to-digital data converters. They are based on a time-interleaving and pipelining successive-approximation-register (SAR) structure. The resulting ADCs require very low power dissipation for medium-speed and medium-accuracy data conversion.
The design and implementation details of a 4-bit time interleaved successive approximation register (SAR) analog to digital converter (ADC) for UWB application is presented in this paper. Major contribution of this paper is the proposal for a novel digital to analog converter (DAC) architecture which reduces the area required for capacitors by a factor of three, while the maximum error due mismatch...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
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