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This paper introduces a new simplified model describing the charge injection induced error in sample and hold circuits. The proposed model has the advantage of a simpler analytical form then the exact model present in literature, while describing the error dependence on all important factors with good accuracy. We also present analytical constant error curves for different parameter combinations.
This paper analysis the charge injection induced error in CMOS switched capacitor circuits. For this purpose, the basic S/H topology is used and an on-off transition model is considered, for both n and p channel switches. The transient error voltage behavior is presented. The final error value dependence on circuit parameters is analyzed and compared with simulation results.
A new mode of MOSFET operation with distributed gate voltage is proposed and a one-dimensional (1D) analytical model presented. Operation in the strong inversion regime of the laterally nonuniform (LNU) long channel devices is analyzed at room temperatures using gradual channel approximation considering carrier transport by drift alone. Models with linearly graded gate voltage show that these four...
With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
Recent silicon process technology advancements have given chip designers integration capabilities never were possible before, and have led to a new wave of complex ASICs (applied specific integrated circuits). These advanced processes come with new challenges. This paper presents some of the challenges in deep submicron technologies, which require new design practices. We demonstrate some issues related...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
This paper presents an analytical modeling of ballistic and quasi-ballistic transport, implemented in Verilog-A environment and used for circuit simulation. Our model is based on the Lundstrompsilas approach and uses an expression of the backscattering coefficient given by the flux method. The model takes also into account short channel effects and tales into account the effects of different scattering...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
This paper brings in three transistor models that may be used for weak inversion design: the EKV model, the ACM model and the BSIM3v3 model. The EKV model is used in modeling of weak inversion to offer an accurate prediction of low-voltage, low-current designs. The ACM model gives equations that avoid non-physical interpolating curves between weak inversion and strong inversion region, with the intensions...
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