The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, a 10-b analog-to-digital converter (referred to as EMADC) for directly monitoring electrical stimulator outputs with voltage from ∼0V up to ∼45V is proposed. A new high voltage (HV) switch for sampling is also proposed. The maximum input voltage for the HV switch is only limited by the drain-to-source breakdown voltages of the HV transistors. The EMADC was implemented in a 0.18μm CMOS...
Miniaturization and form factor reduction in wearable computers leads to enhanced wearability. Power optimization typically translates to form factor reduction, hence of paramount importance. This paper demonstrates power consumption analysis obtained for various operating modes in circuits suitable for wearable computers which are typically equipped with sensors that provide time series data (e.g...
Power efficiency and variability, currently, are the main aspects of concern of nanometer-scale CMOS technology. Both issues have been widely studied and described in the literature, and various options for their independent management are available. Unfortunately, their exacerbation on sub-40 nm processes will require new design solutions for concurrent optimization. This paper moves towards this...
In earlier, Fault Analysis (FA) has been exploited for several aspects of analog and digital testing. These include, test development, Design for Test (DFT) schemes qualification, and fault grading. Higher quality fault analysis will reduce the number of defective chips that slip past the tests and end up in customer's systems. This is commonly referred to as defective parts per million (DPM) that...
There have been many solutions to create a soft error immune SRAM cell. These solutions can be broken down into three categories: a) hardening, b) recovery, c) protection. Hardening techniques insert circuitry in an SRAM cell possibly duplicating the number of transistors. Recovery techniques insert current monitors in SRAMs to detect SEUs and they employ error correcting codes or redundancy to mitigate...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.