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A precise and robust synchronization of a control system of single-phase converters connected to ac power grid is a key factor for proper function of these devices. This paper presents optimization of Second Order General Integrator Phase Locked Loop (SOGI PLL) and its implementation. The SOGI makes it possible to identify the position of either the power grid voltage or current vector in a stationary...
The paper presents hardware design of digital signal processing based PSK demodulator using Costas loop. On the basis of analyzing the mathematical models of Costas loop, a method to model and simulate it by MATLAB is put forward. The design of LPF (low-pass filter), LF (loop filter) and VCO (voltage-controlled oscillator) are researched. It is first simulated using MATLAB in analog domain and then...
This paper deals with the comparison of the analog and digital phase-locked loops that use identical LC VCO. Both circuits were designed and simulated in CMOS AMS 0.35 μm (3.3 V) technology using full-custom technique. The centre frequency of the oscillator is about 1.1 GHz. The analog loop consists of the Gilbert multiplying phase detector and active low-pass filter while digital one is built of...
This paper discusses a new PLL (Phase-Locked-Loop) approach for detection of the fundamental positive-sequence component of three-phase systems. Details about this three-phase PLL structure are provided. The positive sequence detector presented computes inner-products between the input and a locally generated version of the fundamental frequency. The inner-products are used to estimate the phase-angle,...
Time synchronization is a key component in numerous wireless sensor network applications. Most of the current software based time synchronization approaches suffer from communication overhead and lack of scalability. In this paper, we propose a hardware based approach based on voltage controlled crystal oscillator and phase locked loop techniques to achieve and maintain sub microsecond level time...
This paper proposes a new three-phase positive sequence detector. The scheme is based on a stationary reference frame and a Moving Average Filter (MAF) that guarantees the complete cancellation of harmonics and grid imbalances. The performance of the MAF is mathematically analyzed and a proper selection of the optimal filter's window width is realized. The proposed detector operates in open loop and...
Based on simple comparison between a conventional navigation receiver and a GNSS software receiver, a generic GNSS receiver architecture is given, which focuses on the GPS IF signal processing algorithm in the channel. According to the channel states the algorithm falls into four parts: signal acquisition, confirmation, fine frequency estimation and tracking. A frequency domain acquisition based on...
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