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Networks-on-chip (NoCs) have become a new chip design paradigm as the size of transistors continues to shrink. Globally-asynchronous locally-synchronous (GALS) on-chip networks are proposed for solving issues such as large clock tree distribution and signal delay variations. More interestingly, for the GALS networks using m-of-n delay-insensitive interconnect, the asynchronous interconnect not only...
The present work describes the FPGA implementation of a PLL synchronization method and a Space Vector Modulation (SVM) for a Matrix Converter destined to be used in future electric vehicles. The use of this implementation technique has three advantages: first, a rotating frame transformation is used as a phase detector; the implementation of the PLL and SVM is realized in a low-cost FPGA; and third,...
High-accuracy time synchronization is one of the most important issues for basic detector modules (BDMs) in the all-digital PET. The existing synchronization solutions are hard to extend as strict requirement to the wires and interfaces. Once the number of BDM changed, the whole system's synchronization should be rebuilt from the beginning. In this paper, a new high-accuracy time-sync solution based...
The increasing popularity of Software Defined Radio is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. Digital filters are necessary in transmitter / receiver side and FIR filters are often chosen for their beneficial properties against IIR filters. Symbol synchronization subsystem also maintains digital filters for interpolation purpose...
This paper describes the hardware efficient implementation of Non data aided method for Symbol timing Synchronization and Carrier phase synchronization for 16-QAM on Kintex 7 FPGA using a feedback structure. Costas loop is used for Carrier phase synchronization and pre-filtering is done for Symbol timing Synchronization to extract the symbol timing information. The performance of the receiver is tested...
For the upcoming PANDA detector at FAIR (Darmstadt, Germany), various components for timing distribution, control and data acquisition are being constructed. Design objective is to support testing of detector components in a laboratory environment, while keeping it scalable and use hardware platforms and interfaces already agreed on for the final implementation.
The upgrades of the Belle experiment and the KEKB accelerator aim to increase the data set of the experiment by the factor 50. This will be achieved by increasing the luminosity of the accelerator which requires a significant upgrade of the detector. A new pixel detector based on DEPFET technology will be installed to handle the increased reaction rate and provide better vertex resolution. One of...
This paper presents the design and performance of a new readout system for gaseous and silicon detectors built for the Minos nuclear physics experiment. A major constraint was to provide a multi-thousand channel, high performance readout system with low manpower effort and tight cost. This was achieved by the re-use of some earlier ASIC and front-end card (FEC) developments, the design of a new digital...
Zero-Degree Detector (ZDD) is a new Detector of Beijing Electron Spectrometer III (BESIII) for both double gamma event detection and luminosity monitoring to substitute the old luminosity monitor. A new luminosity readout is described in this paper which is designed in double width AMC/MTCA form factor with a large Xilinx Virtex5 FPGA in addition to normal electronic signal formation. A FPGA embedded...
This paper describes the TOTEM Trigger System that is in function at the LHC since 2009. The TOTEM experiment is devoted to the forward hardronic physics at collision energy from 2.7 TeV to 14 TeV. It is composed of three different sub detectors that are placed at 9, 13.5, and 220 m from an interaction point. A fast electronic system is needed to review collisions and to select the relevant ones to...
This paper presents a method which can estimate frequency, power and phase of received signal corrupted with additive white Gaussian noise (AWGN) in large frequency offset environment. Proposed method consists of two loops, each loop is similar to a phase-locked loop (PLL). Proposed structure solves the problems of conventional PLL such as limited estimation range, long settling time, overshoot, high...
The structure of the Physical Layer Frame (PLHFRAME) is flexible for DVB-S2 system. At the receiver, it is critical for decapsulating the frame design. By further analyzing the structure of the PLHFRAME, we find some useful properties and also introduce some optimizations into the algorithm. The algorithm is based on a first order Reed-Muller (RM) code to achieve decapsulating the frame. The design...
A new adaptive full digital bit synchronizer, which uses the structure of digital phase-locked loop comprised of lead-lag phase detector and direct digital synthesizer (DDS) is designed based on FPGA. The synchronizer has adaptive characteristic, so the modified quantities of phase can be self adjustment based on difference of the phase. It has also programmable characteristic, so frequency resolution,...
A telescope for a beam test have been developed. The system is intended to measure the spatial resolution performance of different types of silicon detectors. The telescope has four XY measurement as well as trigger planes (XYT board). It can accommodate up to twelve devices under test (DUT board). The DUT board uses two Beetle ASICs for the readout of chilled DUT, microstrip or pixel silicon detectors...
We report on a Synchronous Ethernet based clock distribution and timestamp synchronization implementation over 1000BASE-T (Gigabit over twisted pair) Ethernet. A central 125 MHz global clock is distributed to all detector modules using only commercial off-the-shelf components. The timestamps generated on different modules has a maximum fixed offset of 24-60 ns (depending on the switch tested), and...
Among other detectors, the T2K neutrino experiment comprises three large time projection chambers segmented into over 124.000 electronics channels. The back-end electronics system is designed to distribute a reference clock to the front-end electronics, aggregate event data over seventy-two 2 Gbps optical links and format events that are sent via a standard PC to the global data acquisition system...
The aim of the AMIGA project (Auger Muons and Infill for the Ground Array) is an investigation of Extensive Air Showers at energies lower than by standard Auger array, where the transition from galactic to extragalactic sources is expected. The Auger array is enlarged by a relatively small dedicated area of surface detectors with nearby buried underground muon counters at half or less the standard...
SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a single event upset (SEU), which is induced by radiation effect. This paper presents a technique for ensuring reliable softcore processor implementation on SRAM-based FPGAs. Although an FPGA is susceptible to SEUs, these faults can be corrected as a result of its reconfigurability. We propose techniques for SEU mitigation and recovery...
In this work, the AR-PET architecture is introduced and described. Its data acquisition system is composed of four layers of data processing with the purpose of computing the parameters as soon as possible to reduce data bandwidth for the next layer. FPGAs were used as main processing devices for the first three layers. The first layer computes pulse energy and timestamp, the second layer computes...
High speed serial interfaces represent the new trend for device-to-device communication. These systems require clock recovery modules to avoid clock forwarding. In this paper we present a high-speed clock recovery method usable with low-cost FPGAs. Our proposed solution features increased speed and reduced size compared to existing designs. The method allows a maximum throughput of 400 Mbps compared...
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