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Software-based self-test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing, a particularly...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
This paper considers an alternative strategy to speed up the circuit simulation. This strategy considers characteristics of simulator users' behaviors and involves two techniques, the incremental simulation and simulation-on-demand (SOD). These techniques are implemented in an "Interactive Simulation Environment" to dramatically accelerate the simulation speed in most practical cases. Also,...
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