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Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
This paper demonstrates a differential current-mode chaos-based circuit used to generate random number sequences, which was implemented on 90 nm CMOS-SOI technology. The proposed design implements an improved and robust chaotic map, and diminishes non-idealities such as asymmetry, offset. Randomness tests were conducted and show the advantages of the differential chaos circuit.
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