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The necessity for distributed parallel multimedia processing capacity in the multimedia-aware cloud derives from the fact that it must provide both data storage and computational resources to the whole number of interconnected users. When an application or a service becomes popular, the underlying system needs to scale up efficiently thus introducing the distributed factor into the overall scheme...
A method of retiming the spatial synchronous dataflow graph (SDF) is proposed, which is based on the SDF representation in the multidimensional space. The dimensions of this space are the spatial coordinate of the processing unit, coordinate of the operator firing and operator type. At the first stage of the datapath synthesis, the operator nodes are placed in the space according to a set of rules...
Computing systems have become increasingly heterogeneous contributing to higher performance and power efficiency. However, this is at the cost of increasing the overall complexity of designing such systems. One key challenge in the design of heterogeneous systems is the efficient scheduling of computational load. To address this challenge, this paper thoroughly analyzes state of the art scheduling...
This paper presents a multi-path delay commutator (MDC) FFT processor for high-speed. The proposed FFT processor can achieve a high throughput by using a parallel datapath scheme and a multi-path delay commutator structure. The proposed processor can provide a low hardware complexity and an efficient scheduling scheme of complex multiplications. The proposed efficient scheduling scheme can reduce...
Energy consumption is a critical issue in embedded systems design. One way of being energy efficient is to complete the execution as early as possible. Multi-threaded processors reduce the execution time by exploiting both the instruction level and thread level parallelism, and offer an effective solution for energy saving. With a typical multi-threaded processor design, whenever the instruction pipeline...
High Level Synthesis (HLS) provides a way to significantly enhance the productivity of embedded system designers, by enabling the automatic or semiautomatic generation of hardware accelerators starting from high level descriptions with (usually software) programming languages. Typical HLS approaches build a centralized Finite State Machine (FSM) to control the generated datapath, performing the operations...
In this paper, we extend the compositional scheduling framework to enable the integration of an existing (legacy) application as a component on a faster processor which needs to be shared with other components. After admission of this application into the framework, the integrated component still has to satisfy its tasks' deadline constraints and it must execute jobs in the same order as it did previously...
In this paper, we concentrate on aspects related to the synthesis of distributed embedded systems consisting of programmable processors and application-specific hardware components. The approach is based on an abstract graph representation that captures, at process level, both dataflow and the flow of control. Our goal is to derive a worst case delay by which the system completes execution, such that...
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