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The impedance of a power-distribution network (PDN) in three-dimensionally stacked chips with multiple through-silicon-via (TSV) connections (a 3D TSV IC) was modeled and analyzed using a power/ground (P/G) TSV array model based on separated P/G TSV and chip-PDN models at frequencies up to 20 GHz. The proposed modeling and analysis methods for the P/G TSV and chip-PDN are fundamental for estimating...
This paper presents the analyses of 3D (3 Dimensional) stacked on-chip PDN (Power Distribution Network) impedances, which are composed with on-chip PDNs and TSV (Through Silicon Via) interconnections, and show the various features depending on on-chip PDN designs and 3D stacked chip configurations. Multi-stacked on-chip PDNs with very large capacitances interacting with even very small inductive TSV...
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