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A 7b 1GS/s CMOS folding ADC is presented. It utilizes improved track-and-hold circuit using simple clock generator and bootstrapped sampling switch, sequential amplifier settling method in amplifier chain. It also uses low-power thermometer-to-binary encoder realized with transmission gate multiplexer and intermediate track-and-hold circuit for high-speed mediumresolution A/D conversion. The proposed...
A novel low-power and high-performance Standard Ternary Inverter (STI) for CMOS technology is proposed in this paper. This inverter could be used as a fundamental block for designing other ternary basic logic gates. This circuit consists of only MOS transistors and capacitors without any area consuming resistors in its structure. Another great advantage of this design in comparison with the other...
In this paper we present a novel 1-bit full adder cell. The cell offer less power consumption in comparison with the conventional and current implementation of the full adder cell, especially at low voltages. All transitions are used for simulation to obtain the delay and the power consumption parameters. Simulation is improved in term of power consumption. The new full adder cell is simulated at...
Power analysis attacks are a common and effective method of defeating cryptographic systems. Many power-analysis-resistant digital circuit techniques have been previously proposed, leaving the circuit designer a myriad of choices without a simple way to compare and contrast the strengths and weaknesses of each technique. In this paper, we compare four promising power-analysis-resistant digital logic...
In this paper we present a low voltage symmetric and bidirectional current mirror based on clocked semi-floating-gate (CSFG) transistors used in low-voltage digital CMOS circuits. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offset voltages are used to shift the effective threshold voltage of the evaluating transistors...
Sigma-Delta modulator ADCs used in signal processing applications are usually implemented by switched-capacitor (SC) circuits and CMOS transmission gates. Clock feed-through effect is one of the main non-ideal parameters existing in SC integrators degrading modulator total SNDR and its linearity. In this paper, a comprehensive analysis of clock feed-through effect on CMOS transmission gates on both...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
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