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In this paper, we consider a wireless network with one full-duplex (FD) base station (BS) and a set of half-duplex (HD) user equipments (UEs). In such scenario, in addition to the self-interference, the co-channel interference from uplink UEs to downlink UEs is the main bottleneck for the network performance. To overcome this, we consider the problem of maximizing the minimum fairness rate among all...
Layout versus Schematic (LVS) is a commonly used technique employed at the design stage to insure the correctness of physical layout. However, as process technologies continually advance, increasingly complex boolean operations are required to produce the desired on-mask patterns, which are frequently optimized to enhance transistor performance and process margin. Design layout which has been verified...
The traditional PID controller parameters are hard to tune timely under the rapid changes of the dynamic network circumstances, which affect the PID algorithm's control effects on network data flows. To alleviate the problem, a novel AQM algorithm based on PID controller is proposed, called the improved expert intelligent PID algorithm (IEI-PID). By combining expert knowledge with PID and adding more...
A variety of tasks in formal verification require finding small or minimal unsatisfiable cores (subsets) of an unsatisfiable set of constraints. This paper proposes two algorithms for finding a minimal unsatisfiable core or, if a time-out occurs, a small non-minimal unsatisfiable core. Our algorithms can be applied to either standard clause-level unsatisfiable core extraction or high-level unsatisfiable...
This paper describes the design, integrated circuit implementation, and experimental evaluation of a novel building block that realizes the combined operations of digital-analogue conversion and FIR filtering (DAFIC). To maximize the advantages of both digital and analogue techniques, the circuit comprises a 4-stage digital delay line providing the input to 4 8-bit algorithmic digital-analogue converters...
We consider the problem of approximating an integer program by first solving its relaxation linear program and "rounding" the resulting solution. For several packing problems, we prove probabilistically that there exists an integer solution close to the optimum of the relaxation solution. We then develop a methodology for converting such a probabilistic existence proof to a deterministic...
In many CAD systems for VLSI design the specification of a layout is internally represented by a set of geometric constraints that take the form of linear inequalities between pairs of layout components. Some of the constraints may be explicitly stated by the circuit designer. Others are internally generated by the CAD system, using the design rules of the fabrication process. Layout compaction is...
The complexity of integrated-circuit chips produced today makes it feasible to build inexpensive, special-purpose subsystems that rapidly solve sophisticated problems on behalf of a general-purpose host computer. This paper contributes to the design methodology of efficient VLSI algorithms. We present a transformation that converts synchronous systems into more time-efficient, systolic implementations...
Minimizing the area of a circuit is an important problem in the domain of Very Large Scale Integration. We use a theoretical VLSI model to reduce this problem to one of laying out a graph, where the transistors and wires of the circuit are identified with the vertices and edges of the graph. We give an algorithm that produces VLSI layouts for classes of graphs that have good separator theorems. We...
We consider the design of integrated circuits to implement arbitrary regular expressions. In general, we may use the McNaughton-Yamada algorithm to convert a regular expression of length n into a nondeterministic finite automaton with at most 2n states and 4n transitions. Instead of converting the nondeterministic device to a deterministic one, we propose two ways of implementing the nondeterministic...
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