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In order to reduce the system computation complexity and delay, we propose a scheme to decrease the iterative time of the carrier synchronization for low-density parity-check (LDPC) codes. The system will stop iteration if the log-likelihood ratio (LLR) message at the output of decoder satisfies the limitary conditions. Simulation results show that the proposed scheme is efficient and there is little...
In this paper, we propose the design method and the structure of a decoder with shortened cyclic code for radio data systems (RDS). Without microprocessor the logic gates are used to implement the hardware of the decoder, moreover, the decoder not only can decode the received message of RDS, but also has the functions of synchronization, error detection and error correction. The proposed decoder includes...
In this paper, a very high-throughput and area efficient hardware decoder of the binary (23, 12, 7) Golay code is presented. The key feature of this proposed algorithm is fast determination of the error positions through the analysis on the weight of syndromes without large operations of finite fields. Comparing with the algorithm using one syndrome, the proposed algorithm is more suitable for the...
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