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Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of system-on-chip (SoC) design in the nanoscale technologies. In this paper, a methodology is presented to develop an efficient routing algorithm for network-on-chip platforms that are specialized for an application or a set of concurrent applications. The proposed routing methodology, based on the hybrid...
In this paper, we have proposed a framework of systems-on-chips clustering in application to complicated sensor networks. The framework can be applied to address the communication issues in distributed and large-scaled sensor nodes in wireless sensor network application. There are two communication categories under consideration, i.e. intra-nodes and inter-nodes. Due to the potentially higher frequency...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed...
Three applications in wireless networks where model-free stochastic learning is applicable, are discussed. The learning based optimization problems are formulated and simulation results are presented. Some open issues are also discussed.
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