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In this paper, the network analog method is developed with a view to applying it to compute quasi-static electrical parameters (matrices of capacitance [Cij], inductance [Lij], conductance [Gij] and resistance [Rij]) of multilayer structures in CMOS technology. Finite-difference method with variable increments is applied to solve Laplacepsilas equation. It involves constructing a network analog having...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the...
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