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The authors propose a high--last with gate-last integration scheme with a chemical oxide interfacial layer (IL). It was found that chemical oxide IL could form Hf-silicate at the high- interface so as to provide us a larger effective value and a smaller equivalent oxide thickness (EOT). It was also found that the larger leakage current density for the samples with chemical oxide IL could...
This paper reviews recent experimental confirmations that the intrinsic radiation robustness of commercial CMOS technologies naturally improves with the down-scaling. When additionally using innovative design techniques, it becomes now possible to assure that performance and radiation-hardness are both met. An illustration is given with an original nano-power and radiation-hardened 8 Mb SRAM designed...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Reliabilities of high-k stacked gate dielectrics are discussed from the viewpoint of the impact of initial traps in high-k layer. TDDB reliability can be explained by the generated subordinate carrier injection (GSCI) model. While initial traps increase the leakage current, they do not degrade the TDDB reliability. In contrast, the BTI reliability is strongly degraded by initial traps.
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