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This paper describes a novel compact voltage reference generator able to provide low voltage and low power operation. The current-mode scheme, designed and simulated in a standard 0.18-μm CMOS technology, uses MOS transistors in sub-threshold to achieve low voltage operation. Post layout simulation results show that the proposed circuit is able to generate a reference voltage of 214.5 mV with a supply...
A novel low-power and high-performance Standard Ternary Inverter (STI) for CMOS technology is proposed in this paper. This inverter could be used as a fundamental block for designing other ternary basic logic gates. This circuit consists of only MOS transistors and capacitors without any area consuming resistors in its structure. Another great advantage of this design in comparison with the other...
This paper proposes a novel floating gate MOSFET (FGMOS) based voltage-controlled grounded resistor (VCGR). The FGMOS is used to cancel the nonlinearity term present in the drain current equation of MOSFET operating in ohmic region. The implementation of nth order tunable high-pass filter using the proposed VCGR is also suggested. The proposed VCGR is simple, compact, accurate, and with low power...
This paper introduces a novel FinFET based domino logic, which exploits the exclusive property of the FinFET device (capacitive coupling between front-gate and back-gate in a four-terminal (4T) FinFET) to simultaneously achieve higher performance and lower power consumption. Using a new implementation of the resistive gate, the keeper device is made weaker at the beginning of the evaluation phase...
A compact high-value floating resistor utilising PMOS devices in the subthreshold region is introduced. A test chip has been fabricated in 0.18 mum CMOS technology to verify the proposed concept. This technique has been applied to design a reconfigurable sixth-order very-low- cutoff-frequency MOSFET-C filter.
In this paper we propose new circuit design options for increasing the ldquoeffectiverdquo failure voltage (Vt2) of both NMOS and PMOS output buffer transistors, thereby helping to protect these fragile devices. Using experimental data, device and circuit simulations we demonstrate how placing a series resistor and either a bias circuit for the buffer gates or secondary ESD diodes may significantly...
A 0.16 mm CMOS Technology has been characterized using SEMATECH ESD Benchmarking test structures. The usefulness of the structures is shown with regard to device layout and process issues. Areas where the structures need improvement are also examined.
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