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The continuous devices shrinking has introduced new challenges to integrated circuit design, mainly to deal with the overall yield loss [1]. Designers start to take into account process variability impact in the early design stages to successful deal with yield loss. Process variability have a critical effect on integrated circuits increasing power consumption to out of design specifications, accelerating...
As the technology continues to shrinks, leakage power is growing at exponential rate due to the aggressive scaling trends of channel lengths, gate oxide thickness, and doping profiles combined with an increasing number of transistors packaged in a single chip. During the physical implementation stages VLSI designs often needs be corrected due to the changes in specification or design rule constraints...
The power optimization of integrated circuits must be observed in all levels of abstraction of the design flow. The traditional standard cell flow don't really takes care of power minimization at physical level, because there is a limited number of logical functions in a cell library, as well a limited number of sizing versions. To really obtain an optimization at physical level, it is needed to allow...
The paper presents a new approach for the physical design of integrated circuits where all logic cells are designed on the fly, without the limitations that exists when using a cell library (number of functions, number of transistors, transistor sizing, area and power consumption). A cell generator allows the automatic design of cells having any transistor network (using simple gates or static CMOS...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit 1GSPS at 1.8 V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further,...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
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