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Recent works demonstrate constant optimizations in the number of transistors necessary to implement some logic functions by using non-series-parallel arrangements. However, these kind of networks can produce non-dual and non-planar structures, which cannot be fully treated by some of the classical algorithms dedicated to placement. In this paper we present two methodologies to place and route non-series-parallel...
The paper presents a new approach for the physical design of integrated circuits where all logic cells are designed on the fly, without the limitations that exists when using a cell library (number of functions, number of transistors, transistor sizing, area and power consumption). A cell generator allows the automatic design of cells having any transistor network (using simple gates or static CMOS...
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