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Content addressable memory (CAM) plays an important role in the performance of many applications such as DCT transforms, processor caches, database accelerators, and network routers because it enables high-speed search operations with hardware acceleration. However, the power consumption of CAM is rather high because within CAM, searching is conducted in parallel for all registered words. Hence, pre-computation-based...
Content-addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due to its ability to improve application performance by using parallel comparison to reduce search time. Although the use of parallel comparison results in reduced search time, it also significantly increases power consumption...
Dynamic power reduction techniques such as sequential clock-gating aim at eliminating inconsequential computation and clock-toggles of the registers. Usually sequential clock-gating opportunities are discovered manually based on certain characteristics of a design (e.g. pipelining). Since manual addition of sequential gating circuitry might change the functionality of the design, sequential equivalence...
Data path is one of the major power consuming parts of the CPU. Low power high performance processors are the demands of the consumers. The current processors in the market provide enhanced performance, but the factor that we consider is the power consumption. The paper focuses on effective power conserving techniques in the data path including gating the data path and reducing the number of bus lines...
Chip multiprocessors (CMPs) have emerged as a primary vehicle for overcoming the limitations of uniprocessor scaling, with power constraints now representing a key factor of CMP design. Recent studies have shown that the on-chip interconnection network (NOC) can consume as much as 36% of overall chip power. To date, researchers have employed several techniques to reduce power consumption in the network,...
This paper addresses the issue of blocking pattern selection to reduce both leakage and peak power consumption during circuit testing using scan-based approach. The blocking pattern is used to prevent the scan-chain transitions to circuit inputs. This though reduces dynamic power significantly, can result in quite an increase in the leakage power and peak power. We have presented a novel approach...
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