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New truncation scheme is proposed for fixed width recursive multipliers. The architecture has been analyzed for errors and hardware savings. Error analysis shows the maximum error bound of approximately 0.6 for one-level fixed width recursive multipliers. An architectural analysis shows complexity saving of approximately 25% and even higher for higher level of recursion. The new scheme exhibits significant...
A 2000 gate high speed Bipolar Uncommitted Logic Array using 3 micrometer minimum feature sizes has been described. The chip comprises 1980 CML gates and 64 I/O cells. Typical gate delay is 6 nanoseconds. Power ?? Delay time produced is 0.5 pJ. A single 5 volt supply powers the chip which is fully T.T.L. compatible.
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