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Integration of lanthanum lutetium oxide (LaLuO3) with a κ value of 30 is demonstrated on high mobility biaxially tensile strained Si (sSi) and compressively strained SiGe for fully depleted n/p-MOSFETs as a gate dielectric. N-MOSFETs on sSi fabricated with a full replacement gate process indicated very good electrical performance with steep subthreshold slopes of ~72 mV/dec and Ion/Ioff ratios up...
Easily integrable cost effective gate first Single Metal Single Dielectric (SMSD) solution based on As implantation into TiN/HfO2 with ~1 nm EOT is presented. A consistent n-type shift of 250 mV down to 35 nm Lg is obtained by As I/I compared to the reference stack. Symmetrical threshold voltages (~ plusmn0.5 V) are met for the bulk planar devices using this technique, which would corresponds to low-V...
Impacts of electron trapping/detrapping on the negative bias temperature instability (NBTI) characteristics in silicon nanowire transistors (SNWTs) with metal gates are experimentally studied in this paper. It is demonstrated that large amounts of as-grown defects, including both electron traps and hole traps, are induced by nanowire structure due to multiple surface crystal orientations of the cylinder...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Since the very beginning of the flash memory era, the market has been dominated by the floating gate technology. However, as floating gate flash continues along a very steep scaling path, more and more barriers start to appear, limiting further scaling possibilities of the technology. At the same time, other concepts are preparing to take over. This paper concentrates on the prospect of high-k materials...
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