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The evolution of the recoverable (R) component of negative-bias temperature instability (NBTI) is examined, as a function of the number of stress and relaxation cycles, for the SiON, HfSiON, and HfO2 p-MOSFETs. At typical NBTI oxide fields (~7 MV/cm), a steady and substantial decrease of the R component in the case of the HfO2 p-MOSFET is observed, while the R component of the SiON and HfSiON p-MOSFETs...
In this paper, we present an approach to analyse the degradation behaviour of the gate dielectric of thousands of MOS transistors simultaneously. Our approach is based on array test structures and automated test systems. The array test structures with a matrix-like arrangement of the MOS devices under test (DUT) have been designed and fabricated in a 130 nm mixed-mode CMOS process. They permit to...
We have developed a novel AlGaN/GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) using stack gate IHD2/Al2O3 structure grown by atomic layer deposition (ALD). The stack gate consists of a thin HfO2 (30Aring) gate dielectric and a thin Al2O3 (20Aring) interfacial passivation layer (IPL). For the 50Aring stack gate, no measurable C-V hysteresis and smaller threshold voltage...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
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