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Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the...
In the paper we describe a method to extract the topography of an impressed current for our bounded electrical impedance tomography (bEIT) studies. The frequency of the impressed current is low (up to a few hundred Hz), and is buried in background EEG and other noise. For the development of the extraction method, special consideration is given to maximize the signal-to-noise ratio. The standard lock-in...
An intensity modulated fiber-optic position sensor, based on a fiber to bundle coupling and a readout system using a CMOS image camera together with fast routines for position extraction and calibration, is experimentally demonstrated. Further, a simulation of the complete sensor system setup is made, and possible sources of error are analyzed experimentally. Our analysis indicates the theoretical...
In this paper, we propose a robust STBC transmission scheme to combat the timing synchronization errors over frequency-selective multiple-access channels. First, the equivalent channel model in the presence of timing synchronization errors is derived and we find that the synchronization errors result in an equivalent channel model with larger number of correlated channel taps. Based on this correlated...
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