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We investigated the impact of oxide liner elastic modulus and thickness on through-silicon via (TSV) Cu pumping and stress. A low-k dielectric liner showed a decrease in residual Cu pumping and TSV stress compared to O3-TEOS SiO2 and ALD SiO2 liners. For TSVs with a post-plating anneal, residual Cu pumping decreases from (102 ± 7) nm to (11 ± 1) nm (99.9th percentile) when the O3-TEOS SiO2 liner thickness...
Thermal stress is induced by high temperature manufacturing processes, due to the mismatch of Coefficient of Thermal Expansion s (CTE) between silicon, dielectric material and copper. In this paper, thermal stress around Through-Silicon-Vias (TSVs) was discussed using 3D FEA transient method. Stress distributions near a TSV and TSVs array were investigated after dielectric liner deposition, barrier...
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