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Different thermal processes and substrates were used to investigate the time evolution of phosphorus loss due to segregation at the Si-SiO2 interface. Dose recovery occurred as phosphorus diffused into bulk silicon during furnace annealing. Dose loss increased when samples were cycled between silicon implantation and rapid thermal annealing (RTA). This implies that transient enhanced diffusion promotes...
We report for the first time experimental investigations on SOI, Si1-xGexOI & GeOI Tunnel FET (TFET). These devices were fabricated using a Fully Depleted SOI CMOS process flow with high k-metal gate stack, enabling 2 decades lower IOFF (~30fA/mum) compared to co-processed CMOS. We successfully solve the TFET bipolar parasitic conduction by a novel TFET architecture, the Drift Tunnel FET (DTFET),...
We demonstrate a self-aligned process for forming fully- depleted SOI MOSFETs with deposited metal-silicon S/D junctions and gate lengths as short as 75 nm. For the devices presented here, the metal S/D regions were formed of deposited Al which is self-aligned to the gate and STI edges, with Si3N4 junction passivation to suppress Fermi-level pinning. Inverse modeling of the electrical data indicates...
Ultra Thin Body Si-On-ONO (UTB SOONO) transistors with ultra thin spacer are successfully demonstrated and evaluated. They have shown increased driving current more than 30% compared with conventional UTB SOONO transistors with thick spacer due to reduced source/drain resistance without short channel effect degradation by using thin spacer. In this paper, it is shown that thin spacer technology is...
We report a novel contact technology comprising Selenium (Se) co-implantation and segregation to reduce Schottky barrier height PhiBn and contact resistance for n-FETs. Introducing Se at the silicide-semiconductor interface pins the Fermi level near the conduction band, and achieves a record low PhiBn of 0.1 eV on Si:C S/D stressors. Comparable sheet resistance and junction leakage are observed with...
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