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The continual downscaling of CMOS transistors, as predicted by Moore's Law, has faced tremendous challenges in terms of performance and cost reduction. Through Silicon Via (TSV) technology provides an alternative "More than Moore" solution for system level integration, resulting in smaller form factor, reduced power consumption and large bandwidth for higher data transfer rate. Via-last...
This paper presents micro fabrication process and wafer-level integration of a silicon carrier, which consists of two Si chips that are bonded together with evaporated AuSn-solder. There are micro fins and channels fabricated in the Si chip and form the embedded cooling layer after bonding. The embedded cooling layer is connected with an inlet and an outlet to form a fluidic path for heat transfer...
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