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Increased system size and a greater reliance on utilizing system parallelism to achieve computational needs, requires innovative system architectures to meet the simulation challenges. As a step towards a new network class of co-processors — intelligent network devices, which manipulate data traversing the data-center network, this paper describes the SHArP technology designed to offload collective...
The rate of increase of silicon capacity in integrated circuits (IC) will enable system integration of several billion transistors to reside on a single chip in the near future. Future system-on-chip (SoC) systems must therefore integrate up to several hundreds of cores within a single chip, and SoC designs will employ on-chip communication networks (NoCs) as a result. This paper discusses the problems...
This paper introduces the Quarc NoC, a novel NoC architecture inspired by the Spidergon NoC. The Quarc scheme significantly outperforms the Spidergon NoC through balancing the traffic which is the result of the modifications applied to the topology and the routing elements.The proposed architecture is highly efficient in performing collective communication operations including broadcast and multicast...
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