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As the design complexity increases dramatically, results of functional simulation are usually checked through only a part of signals during design verification. It is important, therefore, to consider the observability of internal signals for effective checking. This paper proposes a static observability analysis method to automatically select internal observation signals, which improves the quality...
In this paper an analytical extension to the ITRS multi-site efficiency model is proposed to obtain the distribution of multi-site efficiency. Multi-site testing is becoming one of the most popular ways for test time reduction, increasing the test throughput and reducing the overall test cost. In the model, the efficiency of multi-site testing is computed from process parameters (e.g. yield, yield...
In this paper, we introduce a new test paradigm called indirect-access scan test, demonstrated over the HOY test platform [12]. Unlike the traditional ATE-based testing, the test data in this paradigm are sent to the chip under test via packets over a single indirect channel. Although there is extra test time overhead for establishing the store-and-forward communication, it offers almost unlimited...
In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die variations in nanoscale manufacturing process. VP exploits recent breakthroughs in compressed sensing to accurately predict spatial variations from an exceptionally small set of measurement data, thereby reducing the cost of...
This paper discusses the generation of information-rich, arbitrarily-large synthetic data sets which can be used to (a) efficiently learn tests that correlate a set of low-cost measurements to a set of device performances and (b) grade such tests with parts per million (PPM) accuracy. This is achieved by sampling a non-parametric estimate of the joint probability density function of measurements and...
Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test data compression (TDC) schemes and low-power X-filling techniques were proposed to address the above problems. These methods, however, exploit the very same ldquodon't-carerdquo bits in the test cubes to achieve different...
The context of this paper is the dynamic ABV (assertion-based verification) of TLM (Transaction Level Modeling) SystemC specifications, which characterize SoCs at a very high level of abstraction. We use a framework for supervising during the SystemC simulation the verification of temporal properties expressed in the PSL language. The efficiency of this approach can be improved by the selection of...
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