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In order to process network packets at high rates, network functions like routing or firewalling require specialized hardware like TCAMs (Ternary Content Addressable Memories), ASICs (Application Specific Integrated Circuits), or GPUs (Graphics Processing Units). Such hardware must be fast enough to process packets at line rate, and furthermore, it must be programmable in order to update the packet...
The online computational burden associated with the solution of the NMPC optimization problem is a key issue when applying nonlinear model predictive control (MPC) to fast dynamic systems. In order to improve the computation efficiency, a novel hardware implementation method for NMPC on a field programmable gate array (FPGA) chip is proposed. The optimization problem formed by NMPC is solved by particle...
The Sequential Monte Carlo (SMC) method is a simulation-based approach to compute posterior distributions. SMC methods often work well on applications considered intractable by other methods due to high dimensionality, but they are computationally demanding. While SMC has been implemented efficiently on FPGAs, design productivity remains a challenge. This paper introduces a design flow for generating...
This paper describes a scripting engine based on the Python language and the ROSE compiler framework. Our scripting engine supports hardware design involving both syntax-directed transformations such as loop coalescing, and goal-directed transformations such as geometric programming. We show how customizing the composition and parametrization of design transformations can lead to designs with different...
This paper presents several challenges and solutions in designing an efficient Message Passing Interface (MPI) implementation for embedded FPGA applications. Popular MPI implementations are designed for general-purpose computers which have significantly different properties and trade-offs than embedded platforms. Our work focuses on two types of interactions that are not present in typical MPI implementations...
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