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A novel portable hardware architecture of the Elliptic Curve Method of factoring, designed and optimized for application in the relation collection step of the Number Field Sieve, is described and analyzed. A comparison with an earlier proof-of-concept design by Pelzl et al. has been performed, and a substantial improvement has been demonstrated in terms of both the execution time and the area-time...
This paper examines the feasibility of utilizing a grid of asynchronously clocked run-time reconfigurable modules (RTRMs) on a dynamically and partially reconfigurable (DPR) FPGA. In contrast to a synchronously clocked grid studied in research, the design, the implementation, the performance and the resource utilization of an asynchronously clocked grid is shown. Such a run-time reconfigurable (RTR)...
This work presents an architecture to compute matrix inversions in a reconfigurable digital system, benefiting from embedded processing elements present in FPGAs, and using double precision floating point representation. The main module of this system is the processing component for the Gauss-Jordan elimination. This component consists of other smaller arithmetic units, organized in pipeline. These...
The concept of hardware resource virtualization which was initiated in virtual memory organization has recently expanded towards virtualization of computing resources in partially reconfigurable FPGAs. However, this kind of resource virtualization requires mechanisms for flexible allocation/relocation of components associated with data execution processes. The ability for on-chip component relocation...
This paper proposes a novel approach to implement reconfigurable architecture dedicated to acoustic algorithms. To explore different reconfigurable architecture suitable for acoustic algorithms, a methodology called virtual embedded block has been applied to identify suitable building blocks which can be a good candidate to embed into existing reconfigurable devices to increase the performance of...
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