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A novel high performance pipelined implementation architecture for user-defined floating-point complex division is presented. The major part of the proposed algorithm is derived from conventional Goldschmidt division algorithm. This paper first describes related user-defined floating-point arithmetic based on FPGA. Then the core of the complex division: (A+jC)/B is implemented based on the proposed...
High-level synthesis (HLS) is increasingly becoming a mainstream design methodology for FPGAs. Whereas its previous applications were mostly limited to research and simple designs, it is now being used to tape-out real-world chips in production [1]. Advances in compiler and HLS research continue to improve the quality of HLS-generated hardware. Despite this, the ease-of-use of HLS tools remains a...
Redundant number systems provide carry-propagation free arithmetic, so that faster arithmetic circuits can be designed. In this work, an alternative redundant arithmetic based fused multiply-accumulate (MAC) unit is designed especially suitable for 6-input look-up-table (LUT) based FPGAs. By employing only (6, 3) counters in the partial product reduction and accumulate operations, least amount of...
Data conversion operations are important and essential part of floating point units in a processor and typical instructions include conversion between various precisions, integer to floating point and vice versa, floating point to fixed point and vice versa etc. Besides few processors have instructions to round and truncate data, sign injections, move data between co-processors registers and general...
Mapping complex mathematical expressions to DSP blocks through standard inference from pipelined code is inefficient and results in significantly reduced throughput. In this paper, we demonstrate the benefit of considering the structure and pipeline arrangement of DSP blocks during mapping. We have developed a tool that can map mathematical expressions using RTL inference, through high level synthesis...
Aiming at the AVS standard which is the audio and video standard of China, an optimized variable length code decoder is proposed for the AVS standard. The design uses an innovative circular shifter to improve decoding parallelism. It optimizes the VLC tables and uses combinational look-up table circuit to avoid memory access. Self-adaptive pipeline technique is adopted to improve decoding speed. The...
The Department of Electronic Engineering of Beijing Institute of Technology is integrating emerging interconnect technologies with other high-performance technologies to meet the demanding requirement of future, real-time signal processing applications. For next-generation, scalable, modular and adaptable signal-processing system, a universal, flexible and high-performance signal processing module...
This paper studies efficient complex valued matrix manipulations for multi-user STBC-MIMO decoding. A novel method called Alamouti blockwise analytical matrix inversion (ABAMI) is proposed for the inversion of large complex matrices that are based on Alamouti sub-blocks. Another method using a variant of Givens rotation is proposed for fast QR decomposition of this kind of matrices. Our solutions...
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