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In this paper, we design energy efficient Finite Impulse Response (FIR) filter, which is widely used in wireless sensor networks as a signal pre-processing step because sensor nodes require a long working periods. Finite impulse response (FIR) filter is a type of digital filters. Response to a unit impulse is finite in FIR filter. FIR filter avoids the limitation of old parallel algorithm which take...
Power is directly proportional to voltage. In this work, voltage scaling is applied in design of low power Vedic multiplier. There is 86–98% saving in leakage power and 4–9% saving in IOs power, when we scale down voltage from 1.5V to 0.5V. Vedic multiplier has now proven its supremacy on traditional multiplier in terms of performance, speed or delay. There is no research work is going on in energy...
In this work of low power memory design on FPGA, we are using the most energy efficient I/O standard among LVCMOS, HSLVDCI, HSTL, LVDCI_DV2 and SSTL. I/O standard is used to match impedance of transmission line, impedance of port and impedance of memory for avoidance of transmission line reflection. In naming convention of I/O Standard, LV is Low Voltage, HS is High Speed, DV2 is Half Impedance, CMOS...
This paper provides an overview of the power measurement techniques in sensor network localization in which solar charge controlled checks the voltage and current of the battery. This is an ideal low-cost design that could be implemented in many developing countries' the grid energy generators. In this paper, we did work on different frequencies and check the power reduction. It has been observed...
This paper presents a novel approach for an effective and temperature controlled communication between environments by controlling the devices of daily use via internet. This research work is done by designing a key generator for every device that is supposed to be controlled. The generated key is added as an address with the device and can be accessed by internet. For this task, designing of thermally...
In order to fill the research gap of energy efficient hardware design in natural language processing, this project reports the designing of an energy efficient Gurumukhi Unicode Reader on Field Programmable Gate Array (FPGA). To avoid transmission line reflection, a usual problem in hardware design, impedances of transmission line, device and port should be equal. In order to avoid transmission line...
In this paper, we have proposed the design of energy efficient and high frequency frame buffer on 40 nm FPGA. The operational frequency of buffer is kept quite high of 1THz and it has been recorded that we need to optimize power considerations in order to reduce the power consumption. The values are recorded on LVCMOS and LVDCI. For LVCMOS, we recorded that average power consumed is 88W and for LVDCI...
In this work, we are integrating thermal aware design approach in energy efficient Vedic multiplier on FPGA. In the beginning of this universe, Veda describes heat receiving from the Sun god as Suryamrit (Surya i.e. Sun +Amrit i.e. Nectar= Suryamrit i.e. Nectar coming from the Sun God). Now, whole world is feeling anxious about temperature. How our thinking pattern is changing with evolution of mankind?...
In this paper, we analyzed how does life and reliability of an integrated circuit is affected when it is operated in different regions under different temperatures. We have taken Fibonacci generator as our target circuit and LVCMOS as I/O standards. WPA and WPA2 (Wi-Fi Protected Access) key can be generated with Fibonacci generator. Here, thermal efficient green Fibonacci Generator is used to generate...
In design and implementation of energy efficient register, we are using different I/O standard in 28nm Artix-7 FPGA, Verilog, Xilinx ISE 14.6 as simulator and XPower 14.6 as energy estimator and analyzer tool. This register is a building block of energy efficient processor based on LVCMOS (Low Voltage Complementary Metal Oxide I/O, HSTL(High Speed Transistor Logic), HSUL standard in FPGA. This design...
In this paper by using Drive Strength techniques and Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) I/O standards, we have designed energy efficient Frequency Meter in Xilinx ISE 14.4 and implemented on −2 speed grade, XC6VLX75T device and virtex-6 FPGA. We have used four different drive strength that is 2mA, 4mA, 6mA and 8mA and we have taken four different types of LVCMOS that includes...
In design and implementation of energy efficient counter for energy efficient processor, we are using LVCMOS I/O standard in FPGA. CMOS technology is used to achieve energy efficiency with corresponding low voltage. We observe that when counter operates at 1×106MHz device operating frequency, there is 67.42% reduction in clock power and 75.99% reduction in IO power with LVCMOS I/O Standard. In counter,...
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